1. Field of the Invention
The present invention relates generally to power modules and, more particularly, to a family of integrated power modules having a common footprint.
2. Introduction
Conventional networking point-of-load (POL) solutions typically include an external field effect transistor (FET). The size of this external FET is typically based on estimates of worst-case power budgets produced by circuit and board level designers. As is customary, power budgets are propagated through the design process in a worst-case fashion to ensure that the actual power drawn by the finally designed load does not exceed the capacity of the initially designed FET.
If testing of the finally designed load indicates that the power requirement exceeds the capacity of the initially designed FET, then a cascading set of design changes could result due to the change in the size, and hence capacity, of the FET. This propagation of changes is even more pronounced where the FET is integrated into the power module along with the controller. In this scenario, the footprint of the entire power module would need to be modified due to the increase in size of the FET. This change in the footprint of the power module would necessitate large changes in board design to accommodate the new design. In general, the risks associated with late-stage modifications of board designs leads to conservative estimates of the power budget through the design process.
A negative consequence of the use of conservative power estimates is a power module design that greatly exceeds the power requirement of the finally designed load. As a reduction in the size of the FET would also necessitate late-stage design changes, the designer may be forced to use a larger FET than is necessary. This leads to an increase in the costs associated with the end product, and ultimately to the competitiveness of the product in the marketplace. What is needed therefore is a power module design that provides flexibility in the design process.